Hardware Interface
The biphase output is a balanced output, using voltages that are within the RS422/485 receiver range. Hooking up a MAX483 or MAX485 receiver converted these into a nice 5V logic stream that I could capture on the logic analyser.
Biphase Decoding
Firstly we can determine the clock frequency directly from the waveform, which is 31.25kHz.
The biphase data can be decoded by examining the level of the signal 4us (ie quarter of the clock period) after the bit boundary. The bit boundary starts at the first edge and appears on each clock period following this. The diagram shows this.
The data is transmitted with a start bit, 8-bits of data (LSB first) and a parity bit. This is clear from the following logic analyser screen captures.
1. Zoom in operation.
Here's the logic analyser capture (broken into two halves) for the bitstream sent when clicking on the camera 1 zoom in icon:
This can be broken down as follows:
|
1 1 1 1 1 0 1 1 |
Preamble |
0xDF |
|
|
1 |
Start bit |
||
|
1 1 1 0 0 0 0 1 |
Length byte |
0x87 |
|
|
1 |
Parity |
E |
|
|
1 |
Start bit |
||
|
0 0 0 0 0 0 0 0 |
Cam addr L |
0x00 |
|
|
1 |
Parity |
E |
|
|
1 |
Start bit |
||
|
0 0 0 0 0 0 0 0 |
Cam addr H |
0x00 |
|
|
1 |
Parity |
E |
|
|
1 |
Start bit |
||
|
1 0 1 0 0 0 0 0 |
Op Code |
0x05 |
Start/Stop variable speed PTZ |
|
1 |
Parity |
E |
|
|
1 |
Start bit |
||
|
0 0 0 0 1 0 0 0 |
Byte 1 |
0x10 |
Zoom speed bit 0 |
|
0 |
Parity |
O |
|
|
1 |
Start Bit |
||
|
0 0 0 0 0 0 0 0 |
Byte 2 |
0x00 |
Pan/Iris settings |
|
1 |
Parity |
E |
|
|
1 |
Start bit |
||
|
0 0 0 0 0 1 0 0 |
Byte 3 |
0x20 |
Zoom in |
|
0 |
Parity |
O |
|
|
1 |
Start bit |
||
|
0 0 1 1 1 1 0 0 |
Checksum |
0x3C |
|
|
1 |
Parity |
E |
|
|
0 1 |
End of message |
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